SRAM: Auto-Save SMS PAL โ€ข 50Hz โ€ข 313 lines
P1
P2
P1: โ† โ†‘ โ†“ โ†’ = D-Pad | Z = Btn1 | X = Btn2 | Enter = Play/Pause
P2: W/A/S/D = D-Pad | Q = Btn1 | E = Btn2 | R = Pause/NMI
๐Ÿ”ง Debug Panel โ–ผ

๐Ÿงช Fuse Z80 Test Suite

Upload Fuse's tests.in and tests.expected files below (drag & drop or click), then run. Compares final register & memory state (T-state timing & bus events ignored).

๐Ÿ“„ Drop tests.in here or click to upload
๐Ÿ“„ Drop tests.expected here or click to upload

          

๐Ÿฎ JSMoo / SingleStepTests (JSON)

Upload a SingleStepTests / JSMoo per-opcode .json file (e.g. 00.json, cb 46.json) โ€” or a .zip containing many .json files (the whole suite). Runs one instruction per test and compares final registers, WZ & touched memory. Optionally verifies bus cycle events โ€” the [addr, data, "rwmi"] triples (memory & I/O read/write accesses); internal "----" cycles are ignored.

๐Ÿฎ Drop a .json or .zip test file here or click to upload

          

โฑ Frame Timing


        

๐ŸŽจ Border Color Debug


          

๐Ÿ”„ Cycle-Based VDP Status


        

โšก VDP Register Corruption

โ—

            
Log

          

CPU Registers z80


        

Flags

VDP State TMS9918A


        

Disassembly


        

SRAM Persistence


        

Breakpoint

No breakpoint

Memory Viewer


        
No ROM Loaded 0 FPS Target: --Hz Cycles: 0 Mode: -- VDP Line: 0 VDP Corruption: OFF